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Synopsys Professional Services Collaborates with Toshiba to Develop Media Embedded Processor --MeP-- Reference Design Flow
MeP Reference Design Flow Streamlines Design Development Time and
Improves Predictability of Core Implementation
MOUNTAIN VIEW, Calif.—(BUSINESS WIRE)—Oct. 20, 2003—
Synopsys, Inc. (Nasdaq:SNPS), the world leader in semiconductor
design software, today announced that Synopsys' Professional Services
has collaborated with Toshiba to develop the Reference Design Flow for
Toshiba's Media Embedded Processor (MeP) and will provide services to
Toshiba's customers for deployment of the flow. MeP is a soft
(synthesizable) core with a unique configurable microprocessor
architecture that can be customized for high performance multi-media
applications such as video, imaging, audio and networking. The
Reference Design Flow enables developers to evaluate different
architectural configurations of MeP in their SoC designs by more
quickly and accurately estimating the resulting chip performance and
size. The Reference Design Flow then provides an integrated path to
implement the optimal configuration. The MeP's configurability,
combined with the performance and schedule predictability made
possible by the Reference Design Flow, will help ensure MeP licensees
can achieve their design targets prior to silicon manufacturing and
meet their market windows.
The Reference Design Flow is based on Synopsys' best-in-class
tools including, Physical Compiler(R) and PrimeTime(R) from Synopsys'
Galaxy(TM) Design Platform. This RTL-to-GDSII flow offers designers
the ability to optimize their designs for performance, power, or die
area, and to implement them with short turn-around times. Toshiba
provides synthesis scripts for the Reference Design Flow optimized for
the MeP architecture. These scripts leverage Physical Compiler's RTL
Performance Prototyping capability, which allows users to validate
incoming IP against a range of physical implementations and quickly
converge on an architecture that best meets their target design goals.
This leads to faster timing convergence and consequently faster time
to market.
"Providing a proven Reference Design Flow is strategic to
Toshiba's business. The MeP Reference Design Flow developed in
cooperation with Synopsys will allow our customers to meet their
design goals in a short and predictable timeframe," said Tohru
Furuyama, general manager, SoC Research and Development Center,
Toshiba Corporation. "Synopsys Professional Services has great breadth
and depth of understanding of how SoCs are designed and verified
today, including considerable experience with complex implementation
and verification environments. Our ongoing collaboration with Synopsys
will enable us to achieve our goal of making the MeP core as easy to
deploy as an IP library, thereby helping give our partners a
time-to-market advantage."
"The Reference Design Flow improves predictability and
productivity for Toshiba's customers by creating a design environment
in which they can rapidly experiment with, analyze and implement their
MeP-based designs. This is a positive step forward in automation for
the configurable processor market," said John Chilton, senior vice
president and general manager, Solutions Group, Synopsys. "The
collaboration with Toshiba was successful not only in responding to
Toshiba's specific project needs, but also in establishing a robust
and repeatable design flow that can be leveraged by their customers.
We will work with our mutual customers to accelerate the deployment of
their MeP-based designs."
Synthesis scripts for the MeP Reference Design Flow will be
provided through Toshiba's web site. The MeP program provides members
access to a comprehensive set of information to help them evaluate and
design with MeP. As an MeP Alliance Partner, Synopsys offers design
environment support for mutual customers of Toshiba and Synopsys,
including assistance with deploying and executing the MeP Reference
Design Flow for core hardening and SoC integration.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is the world leader in electronic
design automation (EDA) software for semiconductor design. The company
delivers technology-leading semiconductor design and verification
platforms to the global electronics market, enabling the development
of complex systems-on-chips (SoCs). Synopsys also provides
intellectual property and design services to simplify the design
process and accelerate time-to-market for its customers. Synopsys is
headquartered in Mountain View, California and is located in more than
60 offices throughout North America, Europe, Japan and Asia. Visit
Synopsys online at http://www.synopsys.com/.
Forward Looking Statements
This press release contains forward-looking statements within the
meaning of the safe harbor provisions of Section 21E of the Securities
Exchange Act of 1934, including statements regarding the expected
benefits of the MeP Reference Design Flow. These statements are based
on Synopsys' current expectations and beliefs. Actual results could
differ materially from the results implied by these statements as a
result of unforeseen difficulties encountered by customers in
implementing the MeP core in their design and the other factors
contained in Synopsys' Quarterly Report on Form 10-Q for the fiscal
quarter ended July 31, 2003.
Synopsys, Physical Compiler, and PrimeTime are registered
trademarks of Synopsys, Inc., and Galaxy is a trademark of Synopsys.
All other trademarks or registered trademarks mentioned in this
release are the intellectual property of their respective owners.
Contact:
Synopsys, Inc.
Eileen Hunt, 650-584-1669
elhunt@synopsys.com
or
Edelman Public Relations
Pushpita Prasad, 650-429-2723
Pushpita.prasad@edelman.com
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